RISC-V Geekbench 5.4 Preview fails with Illegal Instruction on some chips

Vladimir Smirnov's Avatar

Vladimir Smirnov

28 Jan, 2023 11:27 PM


On some chips, like C910-based one (RVB-ICE devboard) fails on Clang test with Illegal Instruction.

What happens there:
[360510.413653] geekbench_riscv[3157]: unhandled signal 4 code 0x1 at 0x000000000012dd20 in geekbench_riscv64[10000+2ae9000]
[360510.424788] CPU: 0 PID: 3157 Comm: geekbench_riscv Tainted: G O 5.10.4 #2
[360510.433038] epc: 000000000012dd20 ra : 000000000012dd1c sp : 0000003fffeb1690
[360510.440315] gp : 0000000002b13728 tp : 0000003fc1326f80 t0 : 0000000000000001
[360510.447672] t1 : aee08180792ccecc t2 : 0000000000000000 s0 : 0000003fa5242520
[360510.455029] s1 : 0000003fffeb19c8 a0 : 0000003fa5242554 a1 : 0000000002b50010
[360510.462378] a2 : 0000000002b50010 a3 : 0000000000000000 a4 : 0000000000000000
[360510.469727] a5 : 0000000000000000 a6 : 0000000000000007 a7 : 0000000002b9f3b0
[360510.477082] s2 : 0000003fffeb16c8 s3 : 0000003fffeb19c8 s4 : 0000003fffeb1ac8
[360510.484437] s5 : 0000000000000000 s6 : 0000000000000000 s7 : 0000000000000000
[360510.491793] s8 : 0000000000000008 s9 : 0000000005eba940 s10: 0000000002b1bc98
[360510.499146] s11: 0000000002c571d0 t3 : 0000000000000000 t4 : 0000000000000077
[360510.506494] t5 : 000000000000000c t6 : 0000000000000076
[360510.511928] status: 8000000200006020 badaddr: 000000008330000f cause: 0000000000000002

Or if I run under GDB:
(gdb) x/i 0x000000000012dd20
=> 0x12dd20: fence.tso

It could be related to fact that some risc-v doesn't handle unaligned memory access well.

  1. 1 Posted by Vladimir Smirno... on 28 Jan, 2023 11:49 PM

    Vladimir Smirnov's Avatar

    Or actually fence.tso might be not supported by that particular board:

    The optional FENCE.TSO instruction is encoded as a FENCE instruction with fm=1000, predecessor=RW, and successor=RW. FENCE.TSO orders all load operations in its predecessor set before
    all memory operations in its successor set, and all store operations in its predecessor set before all
    store operations in its successor set. This leaves non-AMO store operations in the FENCE.TSO’s
    predecessor set unordered with non-AMO loads in its successor set.
    The FENCE.TSO encoding was added as an optional extension to the original base FENCE
    instruction encoding. The base definition requires that implementations ignore any set bits and
    treat the FENCE as global, and so this is a backwards-compatible extension.

    That is a quote from spec. And as it's optional, it can be ignored by vendor.

  2. Support Staff 2 Posted by John on 05 Feb, 2023 05:39 PM

    John's Avatar

    This is a known issue. Our understanding is that the FENCE.TSO instruction should not crash on boards that support the FENCE instruction but not the FENCE.TSO instruction.

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